1. Field of the Invention
The present invention relates to dynamic RAM (random access memory) and, in particular, to dynamic RAM for reading data out after data buses having a plurality of bus lines are precharged.
2. Description of the Related Art
Conventionally, as dynamic RAM becomes large in capacity, the time required for carrying out a performance test of the RAM has increased significantly, resulting in increased cost. One measure taken against this problem is the parallel test mode. FIG. 1 is a block diagram illustrating a conventional example of dynamic RAM in which performance can be tested by means of a parallel test mode. FIG. 2 is a block diagram illustrating the data bus selector of FIG. 1, and FIG. 3 is a circuit diagram illustrating a basic circuit block of FIG. 2.
The dynamic RAM shown in FIGS. 1 through 3 has four I/O (input/output) terminals for entering the data to be written into memory cell array 6 and sending data therefrom so that four bits may be entered and sent in parallel. Further, the dynamic RAM, in order to transfer data to be written and data to be read out, comprises first data bus 11 (comprising four bus lines DBa1 through DBa4) on the I/O terminals side and second data bus 12 (comprising sixteen bus lines DBb1 through DBb16) on the memory cell array side.
Data input buffer 1 takes in the four-bit data supplied to I/O terminals IO1 through IO4, and transfers it to the corresponding bus lines DBa1 through DBa4 of first data bus 11.
During normal operation (non-test mode), data output buffer 2 transfers the read-out data transferred to the data lines DBa1 through DBa4 of first data bus 11 to corresponding I/O terminals IO1 through IO4. During test mode, four-bit test result signals TF1 through TF4 are emitted from test mode comparator 8 to I/O terminals IO1 through IO4.
During normal operation, data bus select decoder 3 activates each bus selector signal BS1 through BS16 for each bus line DBa1 through DBa4 (for example, referring to FIG. 2, it activates selector signals BS1, BS5, BS9 and BS13 at a time). During the test mode, it activates all selector signals BS1 through BS16 at a time.
Data bus selector 9 controls the connection of bus lines DBa1 through DBa4 of the first data bus 11 and bus lines DBb1 through DBb16 of the second data bus 12 according to bus selector signals BS1 through BS16. A block diagram of data bus selector 9 is illustrated in FIG. 2, and an internal basic circuit block CBxj (j=1 through 16) in FIG. 2 is illustrated in FIG. 3.
Precharger 10 precharges bus lines DBa1 through DBa4 and bus lines DBb1 through DBb16 connected via data bus selector 9 to the level of power supply potential Vcc according to precharge control signal PCx.
Write data buffer 5 supplies the data to be written from bus lines DBb1 through DBb16 of the second data bus 12 to memory cell array 6.
Memory cell array 6 stores the supplied data in memory cells located at an address specified by address signal (X1, . . . , Y1, . . . ), or emits the stored data.
Read-out data buffer 7 transferes the data read from memory cell array 6 to bus lines DBb1 through DBb16 of second bus 12.
Test mode comparator 8 determines whether the four bits in each four-bit unit of the sixteen-bit read-out data are consistent (if they are, the memory cell array is judged as normal, and if not, it is judged as abnormal) and sends this result to test data bus 13 as test result signals TF1 through TF4.
The operation of this dynamic RAM will next be described. The sixteen bus lines DBb1 through DBb16 of second data bus 12 are arranged in four separate groups DBb1-DBb4, DBb5-DBb8, DBb9-DBb12, and DBb13-DBd16. During normal operation, each bus line DBa1 through DBa4 of first data bus 11 is connected to one of the four bus lines within a group of bus lines DBb1 through DBb16 of second data bus 12 by data bus selector 9, and the data supplied from I/O terminals IO1 through IO4 is written into memory cell array 6 four bits by four bits, while the read-out data from the memory cell array 6 is sent from I/O terminals IO1 through IO4 four bits by four bits.
During test mode operation, select signals BS1 through BS16 are all activated, and bus lines DBa1 through DBa4 of first data bus 11 are each connected to all four bus lines in each respective group of bus lines DB1 through DB16 of second data bus 12 so that four sets of the same data are written into and read out from memory cell array 6 by four-bit units (four bits by four bits) entered into test mode comparator 8. Test mode comparator 8 determines whether the data is the same for each four-bit unit or not. If not, the corresponding I/O terminals IO1 through IO4 are switched to the low level via data output buffer 2 in accordance with the corresponding test result signals TF1 through TF4. If the data is the same, the corresponding I/O terminal is switched to the high level.
This test method is called a sixteen-bit parallel test mode because sixteen-bit data is written into and read out from memory cell array 6 in parallel.
During the above-described normal operation and test mode, before data is read out from memory cell array 6, data bus lines DBa1 through DBa4 of first bus 11 and data bus lines DBb1 through DBb16 of second bus 12 are all precharged to the level of the power supply potential Vcc.
During normal operation, the above-described conventional dynamic RAM connects one of data bus lines DBa1 through DBa4 of first data bus 11 with one of data bus lines DBa1 through DBb16 of second data bus 12, and during test mode, it connects one data bus line DBa1 through DBa4 to four data bus lines DBb1 through DBb16 of second data bus 12 to write data into memory cell array 6 and to read data from it after precharging. In other words, the load to data input buffer 1 and precharger 10 is greater during test mode than during normal operation. Therefore, the operating margin during test mode decreases, and the test mode operation is less effective or less reliable.